vishay siliconix dg2015 document number: 71971 s11-1185-rev. c, 13-jun-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 low-voltage, low r on , dual dpdt analog switch description the dg2015 is a dual double-pole/double-throw monolithic cmos analog switch designed for high performance switching of analog signals. combining low power, high speed, low on-resistance and small physical size, the dg2015 is ideal for portable and battery powered applications requiring high per formance and efficient use of board space. the dg2015 is built on vishay siliconix?s low voltage ji2 process. an epitaxial layer pr events latchup. break-before- make is guaranteed. the switch conducts equally well in both directions when on, and blocks up to the power supply level when off. features ? halogen-free according to iec 61249-2-21 definition ? low voltage operation (2.7 v to 3.3 v) ? low on-resistance - r on : 0.85 ? ? 3 db loss at 100 mhz ? fast switching: t on = 40 ns t off = 35 ns ? qfn-16 package ? compliant to rohs directive 2002/95/ec benefits ? reduced power consumption ? high accuracy ? reduced board space ? reduce board space ? ttl/1.8 v logic compatible applications ? cellular phones ? speaker headset switching ? audio and video signal routing ? pcmcia cards ? battery operated systems functional block diagram and pin configuration ina no4 nc2 no2 no3 inb no1 nc4 1 2 3 12 11 10 4 9 5678 16 15 14 13 com2 v+ com3 nc3 nc1 com1 gnd com4 top view dg2015 qfn-16 (4 x 4) truth table logic nc1, 2, 3 and 4 no1, 2, 3 and 4 0onoff 1offon ordering information temp range package part number - 40 c to 85 c 16-pin qfn (4 mm x 4 mm) dg2015dn-t1-e4
www.vishay.com 2 document number: 71971 s11-1185-rev. c, 13-jun-11 vishay siliconix dg2015 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 23.5 mw/c above 70 c. d. manual soldering with iron is not recommended for leadless com ponents. the qfn is a leadless package. the end of the lead te rminal is exposed copper (not plated) as a result of the singulation proce ss in manufacturing. a solder fi llet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter limit unit reference v+ to gnd - 0.3 to + 6 v in, com, nc, no a - 0.3 to (v+ + 0.3) current (any terminal except no, nc or com) 30 ma continuous current (no, nc, or com) 150 peak current (pulsed at 1 ms, 10 % duty cycle) 200 storage temperature (d suffix) - 65 to 150 c package solder reflow conditions d 16-pin qfn (4 mm x 4 mm) 240 power dissipation (packages) b qfn-16 c 1880 mw specifications (v+ = 3 v) test conditions otherwise unless specified v+ = 3 v, 10 %, v in = 0.4 v or 2 v e limits - 40 c to 85 c unit parameter symbol temp. a min. b typ. c max. b analog switch analog signal range d v no , v nc v com full 0 v+ v on-resistance r on v+ = 2.7 v, v com = 0.2 v/1.5 v, i no , i nc = 100 ma room full 0.85 1.6 1.7 ? r on flatness r on flatness v+ = 2.7 v, v com = 0 v to v+, i no , i nc = 100 ma room 0.16 r on match ? r on room 0.15 switch off leakage current i no(off) i nc(off) v+ = 3.3 v v no , v nc = 1 v/3 v, v com = 3 v/1 v room full - 1 - 10 1 10 na i com(off) room full - 1 - 10 1 10 channel-on leakage current i com(on) v+ = 3.3 v, v no , v nc = v com = 1 v/3 v room full - 1 - 10 1 10 digital control input high voltage v inh full 2 v input low voltage v inl full 0.4 input capacitance c in full 4 pf input current i inl or i inh v in = 0 v or v+ full - 1 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 2 v, r l = 300 ? , c l = 35 pf room full 40 65 67 ns turn-off time t off room full 35 60 62 break-before-make time t d full 1 3 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 7 pc off-isolation d oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 67 db crosstalk d x ta l k room - 70 n o , n c off capacitance d c no(off) v in = 0 v or v+, f = 1 mhz room 63 pf c nc(off) room 67 channel-on capacitance d c no(on) room 200 c nc(on room 196
document number: 71971 s11-1185-rev. c, 13-jun-11 www.vishay.com 3 vishay siliconix dg2015 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as de termined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by 5 v leakage testing, not production tested. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. typical characteristics (25 c, unless otherwise noted) specifications (v+ = 3 v) test conditions otherwise unless specified v+ = 3 v, 10 %, v in = 0.4 v or 2 v e limits - 40 c to 85 c unit parameter symbol temp. a min. b typ. c max. b power supply power supply range v+ 2.7 3.3 v power supply current i+ v in = 0 v or v+ full 1 a power consumption p c full 3.3 w r on vs. v com and supply voltage supply current vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v com - analog voltage (v) v+ = 3.0 v, - on-resistance ( ? ) r on t = 25 c i s = 100 ma - 60 - 40 - 20 0 20 40 60 80 100 0.1 100 temperature ( c) 1 10 i+ - supply current (na) v+ = 3 v v in = 0 v r on vs. analog voltage and temperature supply current vs. input switching frequency 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v com - analog voltage (v) 25 c - on-resistance ( ? ) r on v+ = 3 v - 40 c 85 c i s = 100 ma 10 10 k 100 k 10 m 100 1 k 1 m 10 ma 1 ma 100 a 10 a 1 a 10 na 100 pa input switching frequency (hz) i+ - supply current (a) v+ = 3 v 100 na 1 na
www.vishay.com 4 document number: 71971 s11-1185-rev. c, 13-jun-11 vishay siliconix dg2015 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) leakage current vs. temperature switching time vs. temperature switching threshold vs. supply voltage - 60 - 40 - 20 0 20 40 60 80 100 1 temperature ( c) v+ = 3 v 10 1000 100 i no(off) , ii nc(off) i com(on) i com(off) leakage current (pa) 20 30 40 50 60 - 60 - 40 - 20 0 20 40 60 80 100 / t on - switching time ( ? s) t off t off v+ = 3 v temperature ( c) t on v+ = 3 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 01234567 v+ - supply voltage (v) - switching threshold (v) v t leakage vs. analog voltage insertion loss, off-isolation crosstalk vs. frequency charge injection vs. analog voltage - 800 - 600 - 400 - 200 0 200 400 600 800 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v com , v no , v nc - analog voltage (v) leakage current (pa) v+ = 3 v i no(off) , ii nc(off) i com(off) i com(on) - 90 100 k 10 m 10 - 70 - 50 100 m 1 g 1 m frequency (hz) (db) loss, oirr, x talk - 30 - 10 loss oirr x ta l k v+ = 3 v r l = 50 ? 0 5 10 15 20 25 30 0123456 v com - analog voltage (v) q - charge injection (pc) v+ = 3 v
document number: 71971 s11-1185-rev. c, 13-jun-11 www.vishay.com 5 vishay siliconix dg2015 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 ? v out gnd v+ 50 % 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output 0.9 x v out t r < 5 ns t f < 5 ns v inh v inl v out =v com r l r l +r on figure 2. break-before-make interval c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 300 ? v inl v inh figure 3. charge injection off on on in ? v out v out q = ? v out x c l c l = 1 nf r gen v out com v in = 0 ? v+ in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. + nc or no
www.vishay.com 6 document number: 71971 s11-1185-rev. c, 13-jun-11 vishay siliconix dg2015 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71971 . figure 4. off-isolation in gnd nc or no 0v, 2.4 v 10 nf com off isolation = 20 log v com v no/ nc r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
terminal tip 5 index area (d 2 e 2) exposed pad 8 -b- d d/2 e/2 -a- e c aaa 2 x top view aa1 a3 -c- seating plane side view bb dd aa cc detail a c 0.08 nx 9 c ccc // d2 d2/2 detail b (ne-1) x e 6 n l e2/2 e2 detail a 2 1 n-1 n (nd-1) x e 8 bottom view c bbb m a b n b 5 datum a or b n r e terminal tip 5 even terminal/side odd terminal/side detail b e e/2 4 c aaa 2 x package information vishay siliconix document number: 71921 19-aug-02 www.vishay.com 1 qfn?16 (4 4 mm) jedec part number: mo-220
notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. all angels are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 iden tifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a molded or marked feature. the x and y dimens ion will vary according to lead counts. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. 6. nd and ne refer to the number of terminals on the d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. variation hhd is shown for illustration only. 9. coplanarity applies to the exposed heat sink slug as well as the terminals. package information vishay siliconix www.vishay.com 2 document number: 71921 19-aug-02 qfn?16 (4 4 mm) jedec part number: mo-220 millimeters* inches dim min nom max min nom max notes a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0 0.02 0.05 0 0.0008 0.0020 a3 - 0.20 ref - - 0.0079 - aa - 0.345 - - 0.0136 - aaa - 0.25 - - 0.0098 - bb - 0.345 - - 0.0136 - b 0.23 0.30 0.38 0.0091 0.0118 0.0150 5 bbb - 0.10 - - 0.0039 - cc - 0.18 - - 0.0071 - ccc - 0.10 - - 0.0039 - d 4.00 bsc 0.1575 bsc d2 2.00 2.15 2.25 0.0787 0.0846 0.0886 dd - 0.18 - - 0.0071 - e 4.00 bsc 0.1575 bsc e2 2.00 2.15 2.25 0.0787 0.0846 0.0886 e 0.65 bsc 0.0256 bsc l 0.45 0.55 0.65 0.0177 0.0217 0.0256 n 16 16 3, 7 nd - 4 - - 4 - 6 ne - 4 - - 4 - 6 r b(min)/2 - - b(min)/2 - - * use millimeters as the primary measurement. ecn: s-21437?rev. a, 19-aug-02 dwg: 5890
vishay siliconix an505 document number: 74976 19-apr-07 www.vishay.com 1 recommended minimum pads for qfn-16 (4 x 4 mm body) note: qfn-16 (4 x 4) has an exposed center pad that must not come into contact with any metalized structure on the pcb. this area is considered a keep out zone. inches millimeters c1 0.142 3.60 c2 0.142 3.60 e 0.026 0.65 x1 0.014 0.35 x2 0.089 2.25 y1 0.037 0.95 y2 0.089 2.25 1 2 3 4 12 11 10 9 16 15 14 1 3 5 6 7 8 keep o u t zone c1 x2 x1 e y1 c2 y2
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
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